A CMOS imager circuit includes a focal plane array of pixel cells, each one of the cells including a photosensor, for example, a photogate, photoconductor or a photodiode overlying a substrate for accumulating photo-generated charge in the underlying portion of the substrate. Each pixel cell has a readout circuit that includes at least an output field effect transistor formed in the substrate and a charge storage region formed on the substrate connected to the gate of an output transistor. The charge storage region may be constructed as a floating diffusion region. Each pixel may include at least one electronic device such as a transistor for transferring charge from the photosensor to the storage region and one device, also typically a transistor, for resetting the storage region to a predetermined charge level prior to charge transference.
In a CMOS imager, the active elements of a pixel cell perform the necessary functions of: (1) photon to charge conversion; (2) accumulation of image charge; (3) resetting the storage region to a known state before the transfer of charge to it; (4) transfer of charge to the storage region accompanied by charge amplification; (5) selection of a pixel for readout; and (6) output and amplification of a signal representing pixel charge. Photo charge may be amplified when it moves from the initial charge accumulation region to the storage region. The charge at the storage region is typically converted to a pixel output voltage by a source follower output transistor.
CMOS imagers of the type discussed above are generally known as discussed, for example, in U.S. Pat. No. 6,140,630, U.S. Pat. No. 6,376,868, U.S. Pat. No. 6,310,366, U.S. Pat. No. 6,326,652, U.S. Pat. No. 6,204,524 and U.S. Pat. No. 6,333,205, assigned to Micron Technology, Inc., which are hereby incorporated by reference in their entirety.
FIG. 1 illustrates a portion of a conventional CMOS imager 10. The illustrated imager 10 includes a pixel 20, one of many that are in a pixel array (not shown), connected to a column sample and hold circuit 40 by a pixel output line 32. The imager 10 also includes a readout or programmable gain amplifier (PGA) 70 and an analog-to-digital converter (ADC) 80.
The illustrated pixel 20 includes a photosensor 22 (e.g., photodiode, photogate, etc.), transfer transistor 24, floating diffusion region FD, reset transistor 26, source follower transistor 28 and row select transistor 30. FIG. 1 also illustrates parasitic capacitance Cp1 associated with the pixel's 20 substrate. The photosensor 22 is connected to the floating diffusion region FD by the transfer transistor 24 when the transfer transistor 24 is activated by a transfer control signal TX. The reset transistor 26 is connected between the floating diffusion region FD and an array pixel supply voltage Vaa-pix. A reset control signal RST is used to activate the reset transistor 26, which resets the floating diffusion region FD (as is known in the art).
The source follower transistor 28 has its gate connected to the floating diffusion region FD and is connected between the array pixel supply voltage Vaa-pix and the row select transistor 30. The source follower transistor 28 converts the stored charge at the floating diffusion region FD into an electrical output voltage signal. The row select transistor 30 is controllable by a row select signal SELECT for selectively connecting the source follower transistor 28 and its output voltage signal to the pixel output line 32.
The column sample and hold circuit 40 includes a bias transistor 56, controlled by a control voltage Vln_bias, that is used to bias the pixel output line 32. The pixel output line 32 is also connected to a first capacitor 44 thru a sample and hold reset signal switch 42. The sample and hold reset signal switch 42 is controlled by the sample and hold reset control signal SAMPLE_RESET. The pixel output line 32 is also connected to a second capacitor 54 thru a sample and hold pixel signal switch 52. The sample and hold pixel signal switch 52 is controlled by the sample and hold pixel control signal SAMPLE_SIGNAL. The switches 42, 52 are typically MOSFET transistors.
A second terminal of the first capacitor 44 is connected to the amplifier 70 via a first column select switch 50, which is controlled by a column select signal COLUMN_SELECT. The second terminal of the first capacitor 44 is also connected to a clamping voltage VCL via a first clamping switch 46. Similarly, the second terminal of the second capacitor 54 is connected to the amplifier 70 by a second column select switch 60, which is controlled by the column select signal COLUMN_SELECT. The second terminal of the second capacitor 54 is also connected to the clamping voltage VCL by a second clamping switch 48.
The clamping switches 46, 48 are controlled by a clamping control signal CLAMP. As is known in the art, the clamping voltage VCL is used to place a charge on the two capacitors 44, 54 when it is desired to store the reset and pixel signals, respectively (when the appropriate sample and hold control signals SAMPLE_RESET, SAMPLE_SIGNAL are also generated).
Referring to FIGS. 1 and 2, in operation, the row select signal SELECT is driven high, which activates the row select transistor 30. When activated, the row select transistor 30 connects the source follower transistor 28 to the pixel output line 32. The clamping control signal CLAMP is then driven high to activate the clamping switches 46, 48, allowing the clamping voltage VCL to be applied to the second terminal of the sample and hold capacitors 44, 54. The reset signal RST is then pulsed to activate the reset transistor 26, which resets the floating diffusion region FD. The signal on the floating diffusion region FD is then sampled when the sample and hold reset control signal SAMPLE_RESET is pulsed. At this point, the first capacitor 44 stores the pixel reset signal Vrst.
Immediately afterwards, the transfer transistor control signal TX is pulsed, causing charge from the photosensor 22 to be transferred to the floating diffusion region FD. The signal on the floating diffusion region FD is sampled when the sample and hold pixel control signal SAMPLE_SIGNAL is pulsed. At this point, the second capacitor 54 stores a pixel image signal Vsig. A differential signal (Vrst−Vsig) is produced by the differential amplifier 70. The differential signal is digitized by the analog-to-digital converter 80. The analog-to-digital converter 80 supplies the digitized pixel signals to an image processor (not shown), which forms a digital image output.
As can be seen from FIG. 1, most of the pixel readout circuitry is designed to be fully differential to suppress noise (substrate or power supply noise), which could create undesirable image artifacts (e.g., flickering pixels, grainy still images). The readout circuitry for the illustrated four transistor (“4T”) pixel, and known three transistor (“3T”) pixels, however, is single ended. Because the reset and pixel signal levels are sampled at different times, any random noise on the supply or reference lines is superimposed on the signals and inadvertently stored on the sampling capacitors 44, 54.
FIG. 3 illustrates portions of the imager 10 that are subject to substrate noise (e.g., at the floating diffusion region FD in the pixel 20 (arrow A) and the bias transistor 56 in the sample and hold circuitry 40 (arrow B)) and noise on the clamp voltage VCL reference (e.g., at clamping switches 46, 48 (arrow C)). Although not shown, there may also be noise on the array pixel supply voltage Vaa-pix. In operation, if there is noise on the clamp voltage VCL reference, the noise is captured on the respective sampling capacitor 44, 54 when the sample and hold reset control signal SAMPLE_RESET or the sample and hold pixel control signal SAMPLE_SIGNAL turns off.
It is especially difficult to reduce substrate noise when a device or chip uses high speed clocks with large loads or when the device/chip's output pads are switching. To compensate for this, clock switching and output pad switching are typically minimized. Unfortunately, some noise remains and the minimization of the clock and output pad switching puts undesirable constraints on the imager's design.
During the readout operation, the imager may experience pixel-wise random noise and noise that varies across the row of pixels. When a gain is applied to the readout pixel signals, the noise becomes visible, which is undesirable. Accordingly, there is a desire and need to prevent readout noise from impairing acquired imager images.